The density of microelectronic devices on a semiconductor substrate may be increased by decreasing the size or line width of the microelectronic devices. The decrease in line width allows a large number of microelectronic devices to be formed on a semiconductor substrate. As a result, the competing power and speed of semiconductor component may be greatly improved.
In order to decrease the line width of a microelectronic device, the lateral dimensions of conductor, semiconductor and insulator regions forming each microelectronic device must be reduced. One such region much focused on is the formation of a gate in a CMOS transistor. The gate length of a microelectronic device is one of the most critical areas to address if an increase in the density of microelectronic devices is to be successfully achieved.
One problem associated with decreasing the gate length of CMOS transistors is the ability to create an adequate source and drain region of that transistor by subsequent processing steps as gate lengths continue to shrink. Ideally, the conductive regions comprising a source and drain of a transistor should slightly overlap under a gate body to create a transistor with optimal operating characteristics. CMOS transistors exhibiting optimal overlap can achieve the highest drive current and optimal threshold voltages. Overlap occurs because of the diffusion of dopant ions during and after the formation of the conductive source and drain regions.
As dopant ions are implanted into the surface of a substrate the dopant ions decay or diffuse laterally. Because dopant implantations are traditionally aligned at the edges of a gate body, any lateral diffusion in the direction of the gate creates a region of overlap. The shorter the gate length of the microelectronic device, the more detrimental an unoptimized overlap may be to the performance of the microelectronic device. For example, a minimal overlap compared to the total gate length in a 0.5 micron device becomes significant in a sub 0.25 micron device.
One means of optimizing dopant overlap under the gate body is through the creation of a pocket implant region that is doped utilizing a dopant species that counteracts the dopant species used to create the source and drain regions. The primary purpose of pocket implants is to achieve graded doping in the channel region of a device. This graded doping reduces the short channel effects of the device and reduces drive current sensitivity to changes in gate length, thereby improving device performance. The pocket implant is ideally situated just under the gate edge in the same vertical dimension as the overlap that is to be optimized. The dopant used to create the source and drain regions has a concentration gradient such that the concentration of the implant outside the gate is very high and begins to drop exponentially at the gate edge. The pocket implant is designed to counteract to some degree the small dopant concentration that exists inside the gate edges. Pocket implants have been successfully utilized to obtain high drive currents and otherwise desirable performance characteristics in microelectronic devices by optimizing source and drain dopant overlap. Even in smaller device geometries, such as devices using sub 0.25 micron gate lengths, pocket implants have been successfully utilized.
However, no systematic means currently exists for determining which optimal conditions during pocket dopant implantation best optimize source and drain dopant overlap. Currently, for each newly manufactured semiconductor device, with its own specific doping characteristics, device geometries, and operating conditions, a wide range of implant dosages, energies, and angles of implantation must be attempted to create a pocket implant that successfully optimizes source and drain region gate overlap.